Digital Electronics 2023

Answer: (ii) 00101111

Solution: 2₁₆ = 0010₂, F₁₆ = 1111₂. So (2F)₁₆ = 00101111₂

Answer: (ii) Odd number of inputs are 1

Solution: XOR gate outputs 1 when an odd number of its inputs are 1 (for 2-input: when inputs differ).

Answer: (ii) A + B

Solution: A + A'B = A(1 + B) + A'B = A + AB + A'B = A + B(A + A') = A + B

Answer: (ii) Connecting J to K

Solution: When J = K = T, the JK flip-flop toggles when T = 1 and holds when T = 0, which is exactly T flip-flop behavior.

Answer: (iii) 0 to 15

Solution: A 4-bit counter has 2⁴ = 16 states, counting from 0 to 15 (0000 to 1111).

Answer: (iii) 16

Solution: A 4-variable K-map has 2⁴ = 16 cells, representing all possible combinations of 4 variables.

Answer: (ii) 2 select lines

Solution: A 4-to-1 MUX needs 2 select lines since 2² = 4 input selections.

Answer: (ii) A' · B'

Solution: By De Morgan's theorem: (A + B)' = A' · B'. The complement of a sum equals the product of complements.

Answer: (iii) Bidirectional shift register

Solution: A bidirectional shift register can shift data left or right depending on the control signal.

Answer: (ii) 19.53 mV

Solution: Resolution = V_ref / (2ⁿ - 1) = 5 / 255 = 0.01961V ≈ 19.53 mV

Answer:

Answer:

BCD (Binary Coded Decimal): Each decimal digit is represented by its 4-bit binary equivalent.

• Example: (47)₁₀ = 0100 0111 (BCD)
• Range per digit: 0000 (0) to 1001 (9)
• Invalid codes: 1010 to 1111

Excess-3 Code: Add 3 to each decimal digit, then convert to BCD.

• Example: (47)₁₀ → 4+3=7, 7+3=10 → 0111 1010 (Excess-3)
• Self-complementing: 9's complement obtained by inverting bits
• 4 in Excess-3: 0111, complement = 1000 = 5 in Excess-3 (4+5=9) ✓

Gray Code: Only one bit changes between successive values.

Binary to Gray conversion: G(n) = B(n), G(i) = B(i+1) ⊕ B(i)

Answer:

De Morgan's Theorems:

Theorem 1: (A + B)' = A' · B' Proof by truth table:

(A+B)' = A'·B' ✓

Theorem 2: (A · B)' = A' + B' Proof by truth table:

(A·B)' = A'+B' ✓

Simplification of F = A'B'C + A'BC + AB'C + ABC:

F = A'B'C + A'BC + AB'C + ABC F = A'C(B' + B) + AC(B' + B) F = A'C(1) + AC(1) F = A'C + AC F = C(A' + A) F = C(1) F = C

Answer:

K-Map layout (4 variables):

        CD
AB    00  01  11  10
00  |  1 |  1 |  0 |  1 |
01  |  1 |  1 |  0 |  1 |
11  |  1 |  1 |  0 |  1 |
10  |  1 |  1 |  0 |  0 |

Groups formed:

1. Group 1 (8 cells): m(0,1,4,5,8,9,12,13) → cells where D=0 or CD=00,01 → Common: D' (not quite — let me regroup)

Let me re-map:

• m(0)=0000, m(1)=0001, m(2)=0010, m(4)=0100, m(5)=0101
• m(6)=0110, m(8)=1000, m(9)=1001, m(12)=1100, m(13)=1101, m(14)=1110

        CD
AB    00  01  11  10
00  |  1 |  1 |  0 |  1 |   (m0, m1, m3=0, m2)
01  |  1 |  1 |  0 |  1 |   (m4, m5, m7=0, m6)
11  |  1 |  1 |  0 |  1 |   (m12, m13, m15=0, m14)
10  |  1 |  1 |  0 |  0 |   (m8, m9, m11=0, m10=0)

Groups:

1. Column CD=00 (all 4): m(0,4,12,8) → C'D'
2. Column CD=01 (all 4): m(1,5,13,9) → C'D
3. Quad m(0,2,4,6): rows AB=00,01, columns CD=00,10 → A'C'... Wait.

Let me simplify systematically:

• Groups: m(0,1,4,5,8,9,12,13) — 8 cells where C=0 → C'
• Remaining: m(2,6,14)
• m(2,6): A'CD' → pair
• m(6,14): BD'C → pair → BC'... no. m(6)=0110, m(14)=1110 → differ in A → B·C·D'

Final expression:

• Group 1: C' (8 cells)
• Group 2: m(2,6,14) → m(2,6): A'CD', m(6,14): BCD' Actually m(2,6,14) can't form a power-of-2 group directly.
  • m(2,6) = A'CD'
  • m(6,14) = BCD'

F = C' + A'CD' + BCD'

Or simplified: F = C' + CD' (A' + B) = C' + D'(A' + B) · C

Hmm, let's verify: F = C' + CD'B + CD'A'

Answer:

Full Adder: A full adder adds three 1-bit inputs: A, B, and carry-in (Cᵢₙ).

Truth Table:

Expressions:

• Sum = A ⊕ B ⊕ Cᵢₙ
• Cₒᵤₜ = AB + BCᵢₙ + ACᵢₙ = AB + Cᵢₙ(A ⊕ B)

4-bit Binary Adder:

• Four full adders are cascaded
• Inputs: A₃A₂A₁A₀ and B₃B₂B₁B₀
• C₀ (initial carry) = 0
• FA0: A₀+B₀+C₀ → S₀, C₁
• FA1: A₁+B₁+C₁ → S₁, C₂
• FA2: A₂+B₂+C₂ → S₂, C₃
• FA3: A₃+B₃+C₃ → S₃, C₄ (overflow)

Result: S₃S₂S₁S₀ with carry out C₄

Disadvantage: Ripple carry causes delay proportional to number of bits. For n-bit adder, worst-case delay = 2n gate delays.

Answer:

3-to-8 Decoder:

• 3 input lines (A₂, A₁, A₀), 8 output lines (D₀-D₇), 1 enable
• Only one output is active (HIGH) at a time
• Output Dᵢ = 1 when input = i in binary

Truth Table (E=1):

Full Adder using 3-to-8 Decoder: Connect A, B, Cᵢₙ as inputs to the decoder:

• Sum = 1 for minterms (1,2,4,7): Sum = D₁ + D₂ + D₄ + D₇
• Cₒᵤₜ = 1 for minterms (3,5,6,7): Cₒᵤₜ = D₃ + D₅ + D₆ + D₇

OR gates combine the decoder outputs to generate Sum and Carry.

Answer:

SR Flip-Flop:

Characteristic equation: Q(t+1) = S + R'Q, with constraint SR = 0

JK Flip-Flop:

Characteristic equation: Q(t+1) = JQ' + K'Q

D Flip-Flop:

Characteristic equation: Q(t+1) = D

T Flip-Flop:

Characteristic equation: Q(t+1) = T ⊕ Q = TQ' + T'Q

Answer:

State Table: | Present State | Next State | JK values | |Q₂ Q₁ Q₀|Q₂ Q₁ Q₀| J₂K₂ J₁K₁ J₀K₀ | |0 0 0|0 0 1| 0X 0X 1X | |0 0 1|0 1 0| 0X 1X X1 | |0 1 0|0 1 1| 0X X0 1X | |0 1 1|1 0 0| 1X X1 X1 | |1 0 0|1 0 1| X0 0X 1X | |1 0 1|1 1 0| X0 1X X1 | |1 1 0|1 1 1| X0 X0 1X | |1 1 1|0 0 0| X1 X1 X1 |

Simplified using K-maps:

• J₀ = 1, K₀ = 1 (always toggle)
• J₁ = Q₀, K₁ = Q₀
• J₂ = Q₁Q₀, K₂ = Q₁Q₀

Circuit: Three JK flip-flops with:

• FF0: J₀ = K₀ = 1 (toggles every clock)
• FF1: J₁ = K₁ = Q₀ (toggles when Q₀=1)
• FF2: J₂ = K₂ = Q₁·Q₀ (toggles when Q₁Q₀=11)

Answer:

1. SISO (Serial In Serial Out):

• Data enters serially, one bit per clock
• Data exits serially from the last flip-flop
• Takes n clock pulses to load n bits
• Used in: time delay circuits
• Structure: FF₀ → FF₁ → FF₂ → FF₃ → Serial Out

2. SIPO (Serial In Parallel Out):

• Data enters serially through first flip-flop
• All outputs available simultaneously (parallel)
• Takes n clock pulses to load, read in 1 pulse
• Used in: serial-to-parallel conversion
• Structure: Serial In → FF₀ → FF₁ → FF₂ → FF₃ (all Q outputs available)

3. PISO (Parallel In Serial Out):

• All bits loaded simultaneously using LOAD signal
• Data shifts out serially
• Load in 1 pulse, read in n pulses
• Used in: parallel-to-serial conversion
• Structure: D₀,D₁,D₂,D₃ → Load → FF₀ → FF₁ → FF₂ → FF₃ → Serial Out

4. PIPO (Parallel In Parallel Out):

• All bits loaded and read simultaneously
• Fastest operation (1 clock pulse)
• Used in: temporary storage, buffer registers
• Structure: D₀-D₃ loaded into FF₀-FF₃, all Q outputs available immediately

Applications of Shift Registers:

• Data conversion (serial ↔ parallel)
• Delay lines
• Ring counters
• Sequence generators

Answer:

RAM (Random Access Memory):

• Volatile memory — data lost when power off
• Read and write operations
• Used for temporary storage

ROM (Read Only Memory):

• Non-volatile — retains data without power
• Read-only in normal operation
• Types: ROM, PROM, EPROM, EEPROM, Flash

SRAM cell: Uses cross-coupled inverters (bistable latch). Fast access, no refresh needed. Used in L1/L2 cache.

DRAM cell: Stores charge on capacitor. Must be refreshed periodically as charge leaks. Used in main memory (DDR4, DDR5).

Answer:

4-to-1 MUX:

• 4 data inputs (I₀, I₁, I₂, I₃)
• 2 select inputs (S₁, S₀)
• 1 output Y

Expression: Y = S₁'S₀'I₀ + S₁'S₀I₁ + S₁S₀'I₂ + S₁S₀I₃

Gate implementation:

• 4 AND gates (each with 3 inputs)
• 1 OR gate (4 inputs)
• 2 NOT gates (for S₁', S₀')

Implementation of F(A,B,C) = Σm(1,2,6,7) using 4:1 MUX:

Use A and B as select lines (S₁=A, S₀=B):

F = MUX(I₀=C, I₁=C', I₂=0, I₃=1, S₁=A, S₀=B)

Answer:

1-to-4 Demultiplexer: Routes one input to one of 4 outputs based on select lines.

Truth Table (E=1):

Expressions:

• D₀ = S₁'S₀'I
• D₁ = S₁'S₀I
• D₂ = S₁S₀'I
• D₃ = S₁S₀I

Priority Encoder (4-to-2): Encodes the highest priority active input.

D₃ has highest priority. V = valid bit (1 when any input is active).

Expressions:

• A₁ = D₃ + D₂
• A₀ = D₃ + D₁D₂'
• V = D₃ + D₂ + D₁ + D₀

Answer:

R-2R Ladder DAC: Uses only two resistor values (R and 2R) regardless of the number of bits.

Working Principle:

• Binary weighted currents flow through the ladder network
• Each bit controls a switch connecting to either Vref or ground
• The op-amp sums the currents and converts to proportional voltage

Circuit:

• Resistor network with R in series and 2R to ground/switches
• Each bit (MSB to LSB) contributes current proportional to its weight
• MSB contributes Vref/(2R), next bit Vref/(4R), etc.

Output Voltage: V_out = -Rf × Vref/2R × (b_{n-1}/2 + b_{n-2}/4 + ... + b₀/2ⁿ)

For 4-bit DAC: V_out = -Rf × Vref × (8b₃ + 4b₂ + 2b₁ + b₀) / (16R)

Advantages:

1. Only two resistor values needed
2. Easy to fabricate in IC form
3. Better matching of resistors
4. Scalable to any number of bits

Disadvantages:

1. Slower than binary weighted due to more resistors
2. Higher total resistance

Answer:

Successive Approximation ADC (SAR ADC): Converts analog input to digital output by binary search.

Components:

1. SAR (Successive Approximation Register)
2. DAC (Digital-to-Analog Converter)
3. Comparator
4. Clock

Working (for n-bit conversion):

Step 1: Set MSB = 1, all other bits = 0. DAC converts to analog. Step 2: Compare DAC output with input voltage.

• If Vin ≥ VDAC: Keep MSB = 1
• If Vin < VDAC: Reset MSB = 0 Step 3: Set next bit = 1, repeat comparison. Step 4: Continue for all bits from MSB to LSB.

Example (4-bit, Vref=16V, Vin=10.5V):

1. Try 1000 (8V): 10.5 > 8 → Keep, MSB=1
2. Try 1100 (12V): 10.5 < 12 → Reset, bit2=0
3. Try 1010 (10V): 10.5 > 10 → Keep, bit1=1
4. Try 1011 (11V): 10.5 < 11 → Reset, bit0=0 Result: 1010 (10V) — closest digital value

Characteristics:

• Conversion time: n clock cycles (fixed)
• Resolution: Vref / 2ⁿ
• Faster than counter-type ADC
• Most widely used ADC architecture

Answer:

A PLA is a programmable logic device with:

• Programmable AND array (product terms)
• Programmable OR array (sum of products)

Structure:

• Input buffers provide true and complement of inputs
• AND array: Creates product terms (minterms)
• OR array: Combines product terms for each output

Advantages:

• Flexible — both arrays programmable
• Can implement any combinational logic
• Reduces chip count

Disadvantages:

• Slower than PAL (two programmable arrays)
• Higher cost than PAL
• More complex programming

Comparison with PAL:

Answer:

A BCD adder adds two BCD digits (0-9) and produces a BCD result.

Problem: Standard binary addition may give invalid BCD (>9).

Correction: If sum > 9 or carry out = 1, add 6 (0110) to correct.

Example: 7 + 6 = 13

• Binary: 0111 + 0110 = 1101 (13, invalid BCD)
• Since sum > 9, add 6: 1101 + 0110 = 1 0011
• BCD result: 0001 0011 = 13 ✓

Circuit:

1. 4-bit binary adder adds A and B
2. Correction detector: checks if sum > 9 or carry = 1
3. Condition: C₄ + S₃S₂ + S₃S₁ (correction needed)
4. Second 4-bit adder adds 0110 when correction needed

Answer:

A digital comparator compares two binary numbers and indicates their relationship (equal, greater than, or less than).

1-bit Comparator:

• A>B = AB'
• A=B = A⊙B = A'B' + AB (XNOR)
• A<B = A'B

4-bit Comparator (7485): Compares A₃A₂A₁A₀ with B₃B₂B₁B₀ starting from MSB:

• Compare A₃ and B₃ first
• If equal, compare A₂ and B₂
• Continue until difference found

Cascading: Multiple 7485 ICs can be cascaded for comparing larger numbers by connecting outputs of lower stage to cascade inputs of higher stage.

Answer:

A sequence detector is a sequential circuit that detects a specific pattern in a serial input stream.

Example: Detect sequence 1011 (overlapping)

States:

• S₀: Initial (no match)
• S₁: Detected "1"
• S₂: Detected "10"
• S₃: Detected "101"
• S₄: Detected "1011" → Output = 1

State Diagram (Mealy Machine):

• S₀ →(1)→ S₁, S₀ →(0)→ S₀
• S₁ →(0)→ S₂, S₁ →(1)→ S₁
• S₂ →(1)→ S₃, S₂ →(0)→ S₀
• S₃ →(1/output=1)→ S₁, S₃ →(0)→ S₂

Implementation: Use JK or D flip-flops, derive excitation equations from state table.